1. Field of the Invention
The present invention relates to a packaging substrate structure with electronic components embedded therein and a method for manufacturing the same and, more particularly, to a packaging substrate structure with electronic components embedded therein, which exhibits enhanced electrical performance and reliability, and a method for manufacturing the same.
2. Description of Related Art
As the electronic industry develops rapidly, the technology of semiconductor package accordingly moves towards integration and miniaturization so that the demands such as multifunction and high efficiency in electronic devices can be met. In addition, a semiconductor package is usually designed in a form of a multi chip module (MCM) to enhance the performance of a single semiconductor package and thus meet the demands for miniaturization, high capacity and high speed in electronic devices. Since a semiconductor package in a form of a multi chip module (MCM) has a reduced size and enhanced electrical performance, a multi chip module has become a popular package form. Furthermore, circuit boards with many active and passive components and circuit connections thereon have advanced from being single-layered boards to multiple-layered boards to expand wiring layout space in a limited circuit board and to meet the demand of the application of high-density integrated circuits.
With reference to FIG. 1, a flip chip ball grid array (FCBGA) semiconductor package is optimally applied in a high-density multi chip module, which has both a flip-chip and a ball grid array package structure. Herein, the active surface 11a of the chip 11 can be electrically connected to the surface 10a (for adhering a chip) of the packaging substrate 10 by a plurality of solder bumps 12. In addition, according to the design demand, the surface 10a (for adhering a chip) of the packaging substrate 10 can further electrically connect to at least one passive component 14, and a plurality of solder balls 15 can be disposed on the other surface of the packaging substrate 10 to function as I/O joints. The aforementioned structure has become mainstream technology for packaging chips and electronic components.
However, in a flip chip ball grid array package structure, the passive components 14 are disposed outside of the packaging substrate 10 by surface mount technology (SMT). Thereby, when a significant amount of passive components 14 are disposed on the surface of the packaging substrate 10 according to the design demand, it is necessary to increase the surface are of the packaging substrate 10 to dispose the increased passive components 14 thereon. Accordingly, the purpose for miniaturization cannot be achieved. In addition, the number of the passive components 14 is limited to the restricted area of the packaging substrate 10, and thereby the demands for high-density packaging have not been met.
Furthermore, the fact that passive components 14 are disposed on the surface of the packaging substrate 10 causes long transmission paths, large parasitic induction, poor electrical performance and thus the quality of signal transmission is badly influenced. Besides, the passive components 14 disposed on the surface of the packaging substrate 10 make the height of the package structure increase and thus the demand for a light, thin, short and small product cannot be met.
In view of the aforementioned drawbacks, many studies relative to a substrate with electronic components embedded therein have been carried out in recent years. In a conventional lamination method, high dielectric material is laminated between two copper layers and then circuits are formed to fabricate capacitors. FIG. 2 shows a cross-sectional view of a packaging substrate structure with capacitors formed therein by lamination. The method for manufacturing the same is mentioned as follows. A core board 20 having an inner wiring layer 21 comprising an inner electrode plate 211 is first provided. Then, a high dielectric material layer 22 is formed on the inner wiring layer 21, and an outer wiring layer 23 comprising an outer electrode plate 231 is formed on the surface of the high dielectric material layer 22. Accordingly, the whole of the inner electrode plate 211, the outer electrode plate 231 and the high dielectric material layer 22 therebetween can function as a capacitor 27. In addition, the inner wiring layer 21 and the outer wiring layer 23 can electrically connect with each other by plated through holes (PTH) 24. Subsequently, a solder mask 25 is formed and the solder mask 25 has a plurality of openings 251 to expose parts of the outer wiring layer 23 as conductive pads 232.
However, the prior art utilizes a whole piece of high dielectric material layer within a packaging substrate, where the used part of the high dielectric material layer for a capacitor is merely the one between the inner electrode plate and the outer electrode plate, while the unused part of the high dielectric material layer contacts with the circuits, and thereby the prior art has several drawbacks: first, the unused part of the high dielectric material layer causes waste, unfavorable to reducing the cost; second, owing to the poor fluidity and the poor machinability of the high dielectric material, voids and poor uniformity of thickness occur and the quality and capacity value of the capacitor is lowered; third, the mismatch of coefficients of thermal expansion badly influences the reliability of products; fourth, the unused part of the high dielectric material layer contacts the circuits, so that parasitic capacitance occurs which interferes with electrical qualities, such as reduced signal intensity, signal distortion, delayed response and so on; finally, because the electrode plates and the circuits are laid together in a wiring layer, the flexibility of layouts of both the electrode plates and the circuits is compromised.